1. Field of the Invention
The present invention relates generally to data transfer techniques, and more particularly, to such a data transfer technique implemented in a wireless communication device.
2. Background Art
A wireless communication device (WCD) typically includes a modulator-demodulator section (commonly referred to as a “modem”) to modulate signals to be transmitted and demodulate incoming or received signals. A known modem, such as a cellular modem, demodulates incoming or received signals received over one or more external interfaces to produce demodulated data. Then, the modem transfers the demodulated data to a destination device over one or more additional external interfaces.
As received signal data rates increase, the number of transfer operations per unit time required to transfer demodulated data to the one or more additional external interfaces in a timely manner correspondingly increases. Accordingly, data transfer operation efficiency becomes an increasingly important factor in modem design as the received signal data rates increase.
A modem typically includes a modem controller to control operation of the modem. A modern modem controller (such as a Reduced Instruction Set Computer (RISC) processor) is typically capable of transferring data in units of multiple-byte words using multiple-byte transfer operations, such as multiple-byte read and write operations. For example, the modem controller can transfer a multiple-byte data word from a memory to an external interface using multiple-byte read and write operations. However, the modem controller may require the multiple-byte data word to be stored in the memory such that the source address of the data word is aligned with a word address boundary of the memory. In some instances, data bytes to be transferred may not be aligned with the word address boundary, as required. Therefore, there is a need for a mechanism enabling a modem controller to transfer such non-aligned data bytes using multiple-byte read and write operations.
The RISC processor and the memory mentioned above are typically coupled together using a memory bus. A maximum rate at which the memory bus can accommodate data transfers between the memory and the RISC processor, and between any other components similarly coupled to the memory bus (such as the one or more additional external interfaces), is referred to as the memory bus bandwidth. Typically, the RISC processor can utilize substantially all of the memory bus bandwidth. Because of such high RISC processor utilization of the memory bus bandwidth, Direct Memory Access (DMA) techniques for transferring data are undesirable, because such DMA transfers operate by way of “stealing” memory bus bandwidth from the processor (that is, by stealing memory bus read or write transfer cycles), thus reducing RISC processor utilization efficiency.
Therefore, there is a need to implement efficient data transfers using a modem controller so as to avoid the complexities of DMA transfers, such as memory bus cycle stealing, thereby minimizing the total number of memory bus cycles required to effect the data transfers.